General Purpose SOC Components

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  • Secure General Purpose Registers

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    General Purpose Resister Built with Data Protection and Redundancy to Store Mission Critical Information in Hidden and Secure Way.Continue Reading

  • Fault Resistant, High Stable AXI4 Slave to AHB/ APB Slave

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    This is Fault Resistant, High Stable, fully protocol Compiaint AXI4 Slave to AHB/ APB Slave Compliant Protocol Translator Block. It supports all kind of transfers, Split and Retry options.
    It is available in Sync and Async mode.Continue Reading

  • Fault Resistant, High Stable Interrupt Controller

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    This is a Configurable Fault Resistant, High Stable Interrupt Controller on AMBA APB/ AHB Interface with wide range to configure synchronous and asynchronous interrupts across SOC and map Different ISR across them. It has option to control and gather different interrupts and set priorities for each of them.Continue Reading

  • Fault Resistant, High Stable, WatchDog

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    These are Fault Resistant, High Stable, Configurable Watchdog Block on AMBA APB/ AHB Interface with wide configuration option to control a Counters and Wide Option to Generate interrupts and Cascade different timers, service them and generate different resets as well.Continue Reading

  • Fault Resistant, High Stable Timers

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    These are Noise Resistant, High Stable(NRHS), Configurable Timer Block on AMBA APB/ AHB Interface with wide configuration option to control a Timer and Wide Option to Generate interrupts and Cascade different timers, Scale the clock freq, service them and generate different resets as well.Continue Reading

  • Fault Resistant Clock and Reset Monitor

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    This is a Clock and reset monitor block. It monitors clock and reset signals and report if there are changes in clock beyond a certain range of frequencies and glitches on reset signals.

    This IP is built with Fault Resistant technology so it remain stable and right warnings to SOC in case of a Fault Event and Hacking attempts.Continue Reading

  • Interrupt Controller

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    This is a Configurable Interrupt Controller on AMBA APB/ AHB Interface with wide range to configure synchronous and asynchronous interrupts across SOC and map Different ISR across them. It has option to control and gather different interrupts and set priorities for each of themContinue Reading

  • WatchDog

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    These are Configurable Watchdog Block on AMBA APB/ AHB Interface with wide configuration option to control a Counters and Wide Option to Generate interrupts and Cascade different timers, service them and generate different resets as well.Continue Reading

  • Timers

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    These are Configurable Timer Block on AMBA APB/ AHB Interface with wide configuration option to control a Timer and Wide Option to Generate interrupts and Cascade different timers, Scale the clock freq, service them and generate different resets as well.Continue Reading

  • General Purpose I/O(GPIO)

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    This is GPIO Block Configurable on AMBA APB/ AHB Interface with wide configuration option to control a PAD and Wide Option to interface internal Chip Ips and Expose signals in different modes, Options, debounce filtering and much more.Continue Reading

  • AHB Lite Master to AHB Master (AHBLM-to-AHBM)

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    This is fully protocol Compiaint AHB Lite to AHB Block. It supports all kind of transfers, Split and Retry options.
    It is available in Sync and Async Flavour.Continue Reading

  • AHB Master to AXI4 Master

    $500.00 – $15,725.00     Select options

    This is fully protocol Complaint AHB Lite to AXI4 Block.
    Supports all kind of transfers translation.Continue Reading

  • AMBA-AHB Security

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    • Completely Hides the Transactions. No Power Profiling is possible.
    • Hides the Data Completely from Debug by changing Key periodically.
    • Self managed key. Can be randomized further across devices using Random Number generators.
    • Multi level Locking. Multiple master Can operate on single Back Bone with Different Access Levels and Access Regions.

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  • AMBA-AXI Security

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    • Completely Hides the Transactions. No Power Profiling for SPA and DPA is possible once this IP is implemented on SOC.
    • Hides the Data Completely from Debug by changing Key periodically.
    • Self managed key. Can be randomized further across devices using Random Number generators.
    • Multi level Locking. Multiple master Can operate on single Back Bone with Different Access Levels and Access Regions.

    Continue Reading