Showing 1–12 of 46 results
GreenIPCore Fault Resistant Ethernet MACRead more
Fault Resistant Gigabit Ethernet MAC can provide reliable high bandwidth communication in harsh environmental conditions of New Age Applications like –
- Industrial Systems.
- Industry 4.0.
- Space Applications.
i3c Dual Role Master Slave Controller with Optional DMARead more
The I3C Master and Slave is AMBA based IP that is useful in building low Power interfaces through I3C/I2C/SPI/UART.
The IP is I3C Dual Role Master and Slave controller which meets the MIPI I3C standard.
The I3C Dual-Role Master & Slave controller is a highly configurable IP and it can be used to provide I3C connectivity to any device.
Fault Resistant Recovery Companion with Single Sequence Recovery$0.00 – $359,550.00 Select options
1. Scan interfacing Block by request response method.
2. Identifies failure stages.
3. Recovers a Failing device.
4. Resets a Failed Device and bring back to operations.
5. Increases product stability.
6. Fault Resistant IP Technology.
Fault Resistant AES Core$5,000.00 – $119,850.00 Select options
1. Fault Resistant Technology to ensure reliable operation.
2. Compliant to NIST FIPS-197 Advanced Encryption Standard.
3. Can be programmed to encrypt or decrypt a 128-bit blocks.
4. Key Size Supported – 128-bit, 192-bit or 256-bit key.
5. There is parameter option given to select Processing Size.
6. User can select 8bit, 32bit, 64bit and 128bit processing.
AES Core$2,000.00 – $79,900.00 Select options
1. Compliant to NIST FIPS-197 Advanced Encryption Standard.
2. Can be programmed to encrypt or decrypt a 128-bit blocks.
3. 128, 192 and 256-bit Key Size Supported .
4. There is parameter option given to select Processing Size.
5. User can select 8bit, 32bit, 64bit and 128bit processing.
6. Ideal solution for low power applications.
7. Minimum logic resources.
Low Latency Interconnect for AI/ML – Shared Multi Memory Integration Controller (SMMIC)$3,000.00 – $79,900.00 Select options
1.Low Latency Interconnect for AI/ML.
2. Advanced Low Power options.
3. Design Architecture solves Routing Congestion, Delay in Command priority and latency issues.
4. Low Power Edge AI/ML Applications
5. High Performance AI/ML Cloud development.
6. This Product can be generated Online.
SOC Stability in Small PackageView products
Please look into Technology Post “SOC Stability in a Small Package from GreenIPCore” for understanding benefits of this pack. More Info – Please write on [email protected] for more info.
High Stable Fault Resistant Synchronous Clock and Reset GeneratorRead more
Fault Resistant Synchronous Clock and Reset generator to remove all the Clock Domain Crossing and Reset Domain Crossing issues.
Secure General Purpose RegistersRead more
General Purpose Resister Built with Data Protection and Redundancy to Store Mission Critical Information in Hidden and Secure Way.
Data Protection Engine(Obfuscation)Read more
Very Low gate Count, Hardware level, Software Data Isolation and Master level Data Protection Engine using Random Controlled Obfuscation and De-Obfuscation.
RunTime Phase Alignment CircuitRead more
This Block uses Approximate local clock (Receiver Local Clock) and incoming data (Rx Data) and generates a Phase and Frequency Aligned Receiver Clock (which is aligned to Tx Clock) at the receiver end. This Generated Rx Clock at the receiver end is available within one clock duration.
This generated clock is aligned to the transmitter clock. it is generated at the receiver side by receiver clock and receiver data.
Receiver clock can be of +/- 5% off of clock frequency of the transmitted clock and phase shift between clocks is not atall a issue. This block can align that as well.
This IP can operate at GHz ranges and can facilitate to transfer long packets without need of any phase or clock extraction and alignment incorporation.
Fault Resistant AMBA AHB/ AXI Slave Memory ControllerRead more
This is Noise Resistant, Temper Resistant (NR TR), fully protocol Complaint AHB Master/ Slave Memory controller and memory Security Block. It secures data and transfer with use of additional sideband signals on AMBA bus systems. It completely hides AMBA Transfers from debug and SPA/ DPA Analysis, Invasive and Non Invasive attacks.