Soft Digital IP
Following are the key features –
- Technology Independent.
- Highest Operating Frequency.
- Lowest Gate Count.
- Fully Stand compliant.
- Well Proven, Guaranteed Success.
- Well Documented.
- Key Innovation and Disruptive features
- Provide edge to your products in the market.
Showing 1–16 of 21 results
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i3c Dual Role Master Slave Controller with Optional DMA
Read moreThe I3C Master and Slave is AMBA based IP that is useful in building low Power interfaces through I3C/I2C/SPI/UART.
The IP is I3C Dual Role Master and Slave controller which meets the MIPI I3C standard.
The I3C Dual-Role Master & Slave controller is a highly configurable IP and it can be used to provide I3C connectivity to any device.
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High Stable Fault Resistant Synchronous Clock and Reset Generator
Read moreFault Resistant Synchronous Clock and Reset generator to remove all the Clock Domain Crossing and Reset Domain Crossing issues.Continue Reading
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RunTime Phase Alignment Circuit
Read moreThis Block uses Approximate local clock (Receiver Local Clock) and incoming data (Rx Data) and generates a Phase and Frequency Aligned Receiver Clock (which is aligned to Tx Clock) at the receiver end. This Generated Rx Clock at the receiver end is available within one clock duration.
This generated clock is aligned to the transmitter clock. it is generated at the receiver side by receiver clock and receiver data.
Receiver clock can be of +/- 5% off of clock frequency of the transmitted clock and phase shift between clocks is not atall a issue. This block can align that as well.
This IP can operate at GHz ranges and can facilitate to transfer long packets without need of any phase or clock extraction and alignment incorporation.Continue Reading -
Interrupt Controller
Read moreThis is a Configurable Interrupt Controller on AMBA APB/ AHB Interface with wide range to configure synchronous and asynchronous interrupts across SOC and map Different ISR across them. It has option to control and gather different interrupts and set priorities for each of themContinue Reading
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WatchDog
Read moreThese are Configurable Watchdog Block on AMBA APB/ AHB Interface with wide configuration option to control a Counters and Wide Option to Generate interrupts and Cascade different timers, service them and generate different resets as well.Continue Reading
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Timers
Read moreThese are Configurable Timer Block on AMBA APB/ AHB Interface with wide configuration option to control a Timer and Wide Option to Generate interrupts and Cascade different timers, Scale the clock freq, service them and generate different resets as well.Continue Reading
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General Purpose I/O(GPIO)
Read moreThis is GPIO Block Configurable on AMBA APB/ AHB Interface with wide configuration option to control a PAD and Wide Option to interface internal Chip Ips and Expose signals in different modes, Options, debounce filtering and much more.Continue Reading
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AHB Lite Master to AHB Master (AHBLM-to-AHBM)
Read moreThis is fully protocol Compiaint AHB Lite to AHB Block. It supports all kind of transfers, Split and Retry options.
It is available in Sync and Async Flavour.Continue Reading -
Clock Domain Crossing and Reset Domain Crossing Component Package
View productsThis package Contains Wide range of Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) Components. These Component fix all the CDC and RDC issues.Continue Reading
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Reset Sequencer
Read moreConfigurable Programmable Reset Sequence Block to sequence the dependent resets assertion and deassertion in their respective domains.Continue Reading
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Reset Synchronizer
Read moreGeneric Reset Synchronizer Block to synchronize resets.Continue Reading
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Synchronous Clock and Reset Generator
Read moreSynchronous Clock and Reset generator to remove all the Clock Domain Crossing and Reset Domain Crossing issues.Continue Reading
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Multi Bit Control and Data Sync
Read moreThis is generic Multi Bit Control and Data Synchronizers with Configurable Sync Depth and Glitch Filtering flop for Stable Design Operations.Continue Reading
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Pulse Transfer Synchronizer VAST
Read moreAll Range Pulse Transfer Synchronizer with Configurable Sync Depth and Glitch Filtering flop for Stable Design Operations.
it can operate in all frequency ranges from 1:1 async to all combination of clock frequency.Continue Reading
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Pulse Transfer Synchronizer STD
Read morePulse Transfer Synchronizers with Configurable Sync Depth and Glitch Filtering flop for Stable Design Operations.
It can operate in standard clock frequency limitation for Sync to operateContinue Reading
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Multi Stage Flop Synchronizers
Read moreMulti Stage Flop Synchronizers with Configurable Sync Depth and Glitch Filtering flop for rejecting any combinational logic glitches.Continue Reading