Fault Resistant High Stable First In First Out (FIFO) (Sync/Async) with OnChip Dual Port SRAM

Fault Resistant High Stable First In First Out (FIFO) (Sync/Async) with OnChip Dual Port SRAM

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This is a Fault Resistant, High Stable, Generic FIFO with configurable depth, configurable width, and clock domain crossing options. This FIFO access external dual port memory to store data.

Description

Conventional FIFO PROBLEMs – Data can be wrongly transferred across FIFO in certain noisy environment condition and silicon timings variation due to temperature. The read and write pointers implemented within FIFO can jump to wrong value due to Faults. In some extreme cases of clock and timing variation due to temperature, the clock domain crossing implemented within FIFO can pass wrong pointer values. This may result in Wrong data Passed on to read side or Data been dropped while Writing. Figure shown below explains how Noisy environment can disturb the data flow by manipulating Pointer Counters and Pointer passed across to generate full and empty flag. This would end up in making system to malfunction.

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