Showing 1–12 of 17 results
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High Stable Fault Resistant Synchronous Clock and Reset Generator
Read moreFault Resistant Synchronous Clock and Reset generator to remove all the Clock Domain Crossing and Reset Domain Crossing issues.
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RunTime Phase Alignment Circuit
Read moreThis Block uses Approximate local clock (Receiver Local Clock) and incoming data (Rx Data) and generates a Phase and Frequency Aligned Receiver Clock (which is aligned to Tx Clock) at the receiver end. This Generated Rx Clock at the receiver end is available within one clock duration.
This generated clock is aligned to the transmitter clock. it is generated at the receiver side by receiver clock and receiver data.
Receiver clock can be of +/- 5% off of clock frequency of the transmitted clock and phase shift between clocks is not atall a issue. This block can align that as well.
This IP can operate at GHz ranges and can facilitate to transfer long packets without need of any phase or clock extraction and alignment incorporation. -
Fault Resistant, High Stable, Multi-Bit Data Sync
Read moreThis is Noise Resistant, High Stable(NRHS), generic Sync Depth Configurable Data Transfer Block with data Valid.
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Fault Resistant, High Stable, Pulse Transfer Sync
Read moreThis is Fault Resistant, High Stable, generic Sync Depth Configurable Pulse Transfer Synchronizer for control path sync.
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Fault Resistant, High Stable, Multi-Stage Flop Sync
Read moreThis is Fault Resistant, High Stable(NRHS), generic Sync Depth Configurable Multistage Flop Synchronizer for control path sync.
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Fault Resistant, High Stable(NRHS) Elastic Buffer
Read moreThis is a Fault Resistant, High Stable, Generic Elastic Buffer with configurable depth, configurable width. This is capable to transferring data in worst conditions.
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Fault Resistant High Stable First In First Out (FIFO) (Sync/Async) with OnChip Dual Port SRAM
Read moreThis is a Fault Resistant, High Stable, Generic FIFO with configurable depth, configurable width, and clock domain crossing options. This FIFO access external dual port memory to store data.
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Reset Sequencer
Read moreConfigurable Programmable Reset Sequence Block to sequence the dependent resets assertion and deassertion in their respective domains.
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Reset Synchronizer
Read moreGeneric Reset Synchronizer Block to synchronize resets.
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Synchronous Clock and Reset Generator
Read moreSynchronous Clock and Reset generator to remove all the Clock Domain Crossing and Reset Domain Crossing issues.
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Multi Bit Control and Data Sync
Read moreThis is generic Multi Bit Control and Data Synchronizers with Configurable Sync Depth and Glitch Filtering flop for Stable Design Operations.
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Pulse Transfer Synchronizer VAST
Read moreAll Range Pulse Transfer Synchronizer with Configurable Sync Depth and Glitch Filtering flop for Stable Design Operations.
it can operate in all frequency ranges from 1:1 async to all combination of clock frequency.
