Soft Digital Components

Showing 1–12 of 15 results

  • High Stable Noise Resistant Synchronous Clock and Reset Generator

    Synchronous Clock and Reset generator to remove all the Clock Domain Crossing and Reset Domain Crossing issues.

  • RunTime Phase Alignment Circuit

    This Block uses Approximate local clock (Receiver Local Clock) and incoming data (Rx Data) and generates a Phase and Frequency Aligned Receiver Clock (which is aligned to Tx Clock) at the receiver end. This Generated Rx Clock at the receiver end is available within one clock duration.
    This generated clock is aligned to the transmitter clock. it is generated at the receiver side by receiver clock and receiver data.
    Receiver clock can be of +/- 5% off of clock frequency of the transmitted clock and phase shift between clocks is not atall a issue. This block can align that as well.
    This IP can operate at GHz ranges and can facilitate to transfer long packets without need of any phase or clock extraction and alignment incorporation.

  • Clock Domain Crossing and Reset Domain Crossing Component Package

    This package Contains Wide range of Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) Components. These Component fix all the CDC and RDC issues.

  • Reset Sequencer

    Configurable Programmable Reset Sequence Block to sequence the dependent resets assertion and deassertion in their respective domains.

  • Reset Synchronizer

    Generic Reset Synchronizer Block to synchronize resets.

  • Synchronous Clock and Reset Generator

    Synchronous Clock and Reset generator to remove all the Clock Domain Crossing and Reset Domain Crossing issues.

  • Multi Bit Control and Data Sync

    This is generic Multi Bit Control and Data Synchronizers with Configurable Sync Depth and Glitch Filtering flop for Stable Design Operations.

  • Pulse Transfer Synchronizer VAST

    All Range Pulse Transfer Synchronizer with Configurable Sync Depth and Glitch Filtering flop for Stable Design Operations.

    it can operate in all frequency ranges from 1:1 async to all combination of clock frequency.

  • Pulse Transfer Synchronizer STD

    Pulse Transfer Synchronizers with Configurable Sync Depth and Glitch Filtering flop for Stable Design Operations.

    It can operate in standard clock frequency limitation for Sync to operate

  • Multi Stage Flop Synchronizers

    Multi Stage Flop Synchronizers with Configurable Sync Depth and Glitch Filtering flop for rejecting any combinational logic glitches.

  • FIFO Component Package

  • Elastic Buffer (Async)

    This is a Fully Tested, Safety Compliant, High Stable, Technology Independent Elastic Buffer with Support of Safety options.

    It has variety of features. For More details on this product, please email the details needed to start@greenipcore.com.