Automotive

Showing 1–12 of 28 results

  • Low Latency Interconnect for AI/ML – Shared Multi Memory Integration Controller (SMMIC)

    Low Latency Interconnect for AI/ML developed with Advanced Low Power methods and Design Architecture solves Routing Congestion, Delay in Command priority and latency issues. Low Power Edge AI/ML Applications and High Performance AI/ML Cloud development.

    Shared Multi Memory Integration Controller(SMMIC) is a memory controller with option to have more than one masters connected to access a memory. And on the memory side, it enables user to  connect more than one memory clubbed together to make a bigger memory. In this way smaller memory segment are created to enable users to make much bigger memory system.

    This Product can be generated Online. Please Login to access Configuration options and generation options.

  • SOC Stability in Small Package

  • High Stable Noise Resistant Synchronous Clock and Reset Generator

    Synchronous Clock and Reset generator to remove all the Clock Domain Crossing and Reset Domain Crossing issues.

  • Secure General Purpose Registers

    General Purpose Resister Built with Data Protection and Redundancy to Store Mission Critical Information in Hidden and Secure Way.

  • Data Protection Engine(Obfuscation)

    Very Low gate Count, Hardware level, Software Data Isolation and Master level Data Protection Engine using Random Controlled Obfuscation and De-Obfuscation.

  • Placeholder

    Temper Resistant AMBA AHB/ AXI Slave Memory Controller

    This is Noise Resistant, Temper Resistant (NR TR), fully protocol Complaint AHB Master/ Slave Memory controller and memory Security Block. It secures data and transfer with use of additional sideband signals on AMBA bus systems. It completely hides AMBA Transfers from debug and SPA/ DPA Analysis, Invasive and Non Invasive attacks.

  • Placeholder

    Noise Resistant, High Stable(NRHS), AMBA AHB/ AXI Master/ Slave Security Block

    This is Noise Resistant, High Stable(NRHS), fully protocol Compiaint AHB Master/ Slave Security Block. It secures data and transfer with use of additional sideband signals on AMBA bus systems. It completely hides AMBA Transfers from debug and SPA/ DPA Analysis, Invasive and Non Invasive attacks.

  • Noise Resistant, High Stable(NRHS), AXI4 Slave to AHB/ APB Slave

    This is Noise Resistant, High Stable(NRHS), fully protocol Compiaint AXI4 Slave to AHB/ APB Slave Compliant Protocol Translator Block. It supports all kind of transfers, Split and Retry options.
    It is avaliable in Sync and Async Flavour.

  • Noise Resistant, High Stable(NRHS), Interrupt Controller

    This is a Configurable Noise Resistant, High Stable(NRHS) Interrupt Controller on AMBA APB/ AHB Interface with wide range to configure synchronous and asynchronous interrupts across SOC and map Different ISR across them. It has option to control and gather different interrupts and set priorities for each of them.

  • Noise Resistant, High Stable(NRHS), WatchDog

    These are Noise Resistant, High Stable(NRHS), Configurable Watchdog Block on AMBA APB/ AHB Interface with wide configuration option to control a Counters and Wide Option to Generate interrupts and Cascade different timers, service them and generate different resets as well.

  • Noise Resistant, High Stable(NRHS), Timers

    These are Noise Resistant, High Stable(NRHS), Configurable Timer Block on AMBA APB/ AHB Interface with wide configuration option to control a Timer and Wide Option to Generate interrupts and Cascade different timers, Scale the clock freq, service them and generate different resets as well.

  • Synchronous Clock and reset Monitor

    This is a Clock and reset monitor block. It monitors clock and reset signals and report if there are changes in clock beyond a certain range of frequencies and glitches on reset signals.