AI/ML

Showing 1–12 of 16 results

  • Low Latency Interconnect for AI/ML – Shared Multi Memory Integration Controller (SMMIC)

    Low Latency Interconnect for AI/ML developed with Advanced Low Power methods and Design Architecture solves Routing Congestion, Delay in Command priority and latency issues. Low Power Edge AI/ML Applications and High Performance AI/ML Cloud development.

    Shared Multi Memory Integration Controller(SMMIC) is a memory controller with option to have more than one masters connected to access a memory. And on the memory side, it enables user to  connect more than one memory clubbed together to make a bigger memory. In this way smaller memory segment are created to enable users to make much bigger memory system.

    This Product can be generated Online. Please Login to access Configuration options and generation options.

  • AXI4 Slave to APB Slave

    This is fully protocol Compiaint AXI4 Slave to APB Slave Compliant Protocol Translator Block. It supports all kind of transfers. It is available in Sync and Async Flavour.

  • AXI4 Slave to AHB Slave

    This is fully protocol Complaint AXI4 Slave to AHB Slave Compliant Protocol Translator Block. It supports all kind of transfers, Split and Retry options. It is available in Sync and Async Flavour.

  • Interrupt Controller

    This is a Configurable Interrupt Controller on AMBA APB/ AHB Interface with wide range to configure synchronous and asynchronous interrupts across SOC and map Different ISR across them. It has option to control and gather different interrupts and set priorities for each of them

  • WatchDog

    These are Configurable Watchdog Block on AMBA APB/ AHB Interface with wide configuration option to control a Counters and Wide Option to Generate interrupts and Cascade different timers, service them and generate different resets as well.

  • Timers

    These are Configurable Timer Block on AMBA APB/ AHB Interface with wide configuration option to control a Timer and Wide Option to Generate interrupts and Cascade different timers, Scale the clock freq, service them and generate different resets as well.

  • General Purpose I/O(GPIO)

    This is GPIO Block Configurable on AMBA APB/ AHB Interface with wide configuration option to control a PAD and Wide Option to interface internal Chip Ips and Expose signals in different modes, Options, debounce filtering and much more.

  • AHB Lite Master to AHB Master (AHBLM-to-AHBM)

    This is fully protocol Compiaint AHB Lite to AHB Block. It supports all kind of transfers, Split and Retry options.
    It is available in Sync and Async Flavour.

  • Clock Domain Crossing and Reset Domain Crossing Component Package

    This package Contains Wide range of Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) Components. These Component fix all the CDC and RDC issues.

  • Reset Sequencer

    Configurable Programmable Reset Sequence Block to sequence the dependent resets assertion and deassertion in their respective domains.

  • Synchronous Clock and Reset Generator

    Synchronous Clock and Reset generator to remove all the Clock Domain Crossing and Reset Domain Crossing issues.

  • Multi Bit Control and Data Sync

    This is generic Multi Bit Control and Data Synchronizers with Configurable Sync Depth and Glitch Filtering flop for Stable Design Operations.