This is Noise Resistant, High Stable(NRHS), generic Sync Depth Configurable Data Transfer Block with data Valid.
- Glitch Filtering flop for rejecting any combinational logic glitches.
- Synchronization as per Standard Sync Method.
- Parameterised Sync Depth Selection.
- Identifiable Flop Names to detect Sync Flops without dependent on Tools and Constraints at later stage of design cycles.
- Technology Independent and tool independent function.
- Using Stable and Tested Standard block decrease time to clean up CDC issues in later stages.
- Standard Synchronizer Flops and Identifiable Signal names make it much easy to identify and extract list of synchronizers. One need not to depend on tools and iterations across them.
- Makes IP More stable to operate.
Deliverables list –
- Source Code in verilog.
- Test Bench.
- Simulation Scripts.
- Synthesys scripts.
- User Guide.
Internal IP Component Block can be used inside any IP/SOC.
More Info –
Please write on email@example.com for more info.